The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures involving a field-effect transistor and methods for forming a structure that involves a field-effect transistor.
Device structures for a field-effect transistor include a source, a drain, a channel situated between the source and drain, and a gate structure including a gate electrode and a gate dielectric separating the gate electrode from the channel. A gate voltage applied to the gate electrode is used to provide switching that selectively connects the source and drain to each other through the channel. The channel of a planar field-effect transistor is located beneath the top surface of a substrate on which the gate structure is supported.
A fin-type field-effect transistor (FinFET) is a non-planar device structure that may be more densely packed in an integrated circuit than planar field-effect transistors. A FinFET may include a fin consisting of a body of semiconductor material, heavily-doped source/drain regions formed in sections of the body, and a gate electrode that wraps about a channel located in the fin body between the source/drain regions. The arrangement between the gate structure and fin improves control over the channel and reduces the leakage current when the FinFET is in its' off state. This, in turn, enables the use of lower threshold voltages, and results in improved performance and lower power consumption.
A gate electrode is usually formed initially as a line-type structure that extends across multiple spaced-apart active regions and isolation regions included in the substrate between these spaced-apart active regions. A gate electrode is patterned so as to have a desired critical dimension, i.e., the dimension of gate electrode corresponding to a “gate length” (or direction of current travel) of the finished field-effect transistor. The initially-patterned gate electrode may be cut by performing an etching process to define gate electrodes having a desired length in a “gate-width” direction of the transistor device. This results in rectangular-shaped gate electrodes, when viewed from above, having the desired dimensions in the gate-length and gate-width directions.
The gate cut may be performed after the interlayer dielectric fill is performed and the gate electrode is revealed by polishing for removal to form the gate cut. Critical gate cuts are dimensionally small in in comparison with non-critical gate cuts. As fin pitch scales downward, providing a critical gate cut at locations between fins presents challenges with respect to process margin. Conventional gate cut patterning and etching process, which merely rely upon a masked etching process, may cause damage to the fins and to the interlayer dielectric layer, especially for critical gate cuts of small critical dimension.
Improved structures involving a field-effect transistor and methods for forming a structure that involves a field-effect transistor are needed.